After room-temperature bonding and subsequent annealing the device wafer of the bonded pair usually needs to be thinned over the entire wafer. Device layer thickness and its uniformity requirements vary with applications. Shown in Table 7.1 are typical specifications of the device layers for sensor, bipolar power device, high speed bipolar and BiCMOS, and CMOS VLSI applications. So far there are basically two approaches to realize the uniform thinning of the device wafer of a bonded pair: 1) mechanical thinning with possibly subsequent refinement by local plasma etching or polishing and 2) layer transferring associated with etch-stop or layer-splitting methods. The applications of these thinning methods are indicated in Table 7.1. We will discuss these thinning technologies in following sections.
Currently, mechanical thinning technology can routinely produce thick device layers (> 1 µm) with a thickness variation of 0.5 µm (7.1, 7.2). If followed by a local polishing or plasma etching, the device layer with thickness down to less than 0.1 µm with less than 10% thickness variation for main stream VLSI CMOS can be realized (7.3). Up to now there are two main layer transfer technologies: 1) selective chemical etching and 2) splitting of an H-implanted layer from the device wafer (7.4). Both technologies have demonstrated the ability to meet the VLSI CMOS requirements.
Table 7.1 Typical requirements of silicon device layers by various applications and the
corresponding thinning technologies
| Sensors | Bipolar & power device | High speed bipolar, BiCMOS | CMOS VLSI | |
|---|---|---|---|---|
| Silicon layer thickness | 1 - 10 µm | 4 - 100 µm | 1 - 2 µm | 0.1 - 0.05 µm |
| Silicon layer thickness uniformity | ± 1 µm | ± 0.5 µm | ± 0.1 µm | ± 5% |
| Thinning technology | Mechanical thinning | Local polishing or etching, or layer transferring | ||
7.1.1 Chemical-mechanical polishing (CMP)
State of the art mechanical thinning approach consists of grinding technology and chemical-mechanical polishing (CMP) technology. Lapping is now being replaced by grinding due to tighter control of the thickness and lower subsurface damage. During grinding operation, the device wafer is thinned using the back of the handle wafer as a reference. Therefore, the handle wafers should be as flat as possible. The silicon is removed from the device wafer by a grind wheel with diamond or silica particles to the total thickness which is the sum of the device layer thickness and the handle wafer thickness. The subsurface damage is in the order of a few microns to the submicron range depending on the grinder configuration used. After grinding and the removal of subsurface damage by chemical etching, chemical-mechanical polishing is used to achieve a smooth surface and a desired thickness. The CMP principle and the resulting surface quality have been described in Chapter 5. As mentioned in Chapter 5, multiple wafer polishers are not suitable for thinning of the bonded wafers due to poor thickness control within a batch. Instead, single wafer polishers have to be used. At the present, mechanical thinning can offer device layers thicker than 1 µm with a thickness variation of 0.5 µm.
7.1.2 Refinement by local thinning
After mechanical thinning the device layer can be further thinned to meet VLSI CMOS requirements by a local polishing or a local plasma etching. A high density film thickness map with sufficient spatial resolution is first produced and then a localized polish pad or plasma is moved across the surface of the wafer varying dwell time inversely to the local thickness of the device layer to mechanically or chemically thin and uniform the device thickness (7.3, 7.5). Since the effective removal rates are very low, the local polish technique has not been widely adapted. However, the local plasma etching method has found its way to production (7.5).
For thin SOI (Silicon-On-Insulator) fabrication, a thickness map of the initial SOI layer with a 64 x 64 point array is obtained by using a visible reflectance technique with a thickness resolution of better than 10Å. Conventional instruments use a visible to near-infrared broadband light source and a microscope objective to illuminate a small sample area on the wafer. Employing a grating to disperse the reflected light onto a one-dimensional detector array, the detector output is serially processed by a computer to determine film thickness by pattern match to stored spectral signatures corresponding to known film thicknesses. It will take over 100 minutes to measure a 20 x 20 point array. A new advanced technique has been developed to speed up the measurements. The broadband light source is sequentially filtered and fully illuminates the wafer. The reflected light is imaged onto a two-dimensional CCD array whose output is parallelly processed to yield a 64 x 64 array of measurements in less than 1 minute. The buried oxide thickness is also measured.
Having a map of film thickness and the stationary plasma etch profile, the etching time for each position on the wafer can be obtained to achieve a desirable uniform thickness. The dwell times are converted into scanning stage commands. The wafer is scanned under the plasma such that the etch area is local at a time and material removal is controlled by the computer scan commands. Measuring and etching can be iterated for more stringent tolerances. Fig. 7.1 is a schematic illustration of the thinning process (7.5). With this process, SOI layer thicknesses less than 1000 Å with a uniformity better than 10% have been obtained. The physical properties of resultant SOI layers such as crystal defects, surface impurities and surface microroughness have been evaluated. It appears that the plasma process does not noticeably degrade the intrinsic quality of the original bonded silicon layers.
In order to achieve device layers with thickness specifications required by VLSI CMOS by mechanical thinning approach, polish-stop technology has also been developed. The polish stop method employes a selective polishing effect in which a predefined pattern onto the device wafer with a material having a polishing rate much lower than silicon. During the thinning process the polishing stops when the polish-stop is reached. This approach leads to application-specific wafers rather than wafers for general applications. Fig. 7.2 shows schematically a representative polish-stop approach (7.6). In this process, the thermal oxide is selectively grown on the device wafer by a standard LOCOS (LOCal Oxidation of Silicon) process using nitride as a mask during the oxidation. PECVD (Plasma Enhanced Chemical Vapor deposition) oxide is then deposited on the device wafer and smoothened. A handle wafer is subsequently bonded to this CVD oxide. The device wafer is ground to a few microns. Final polishing stops when the oxide polish-stop is reached which results in the device islands with thickness equal to the thickness of the oxide. In practice, the thickness variation of the device islands depends on the size of the silicon islands. As the silicon island size gets larger, the thickness variation increases. For silicon islands with an area of 20 by 20 µm device layers with a thickness of (600 ± 80) Å was demonstrated (7.6). Polishing selectivity is a function of many polishing parameters such as pressure, pH value, silica concentration, viscosity and flow rate of slurry, temperature, etc. Therefore, the polishing process should be optimized to stop on the specific material which is designed for the polish-stop. Table 7.2 gives typical CMP polishing selectivities to silicon of thermal oxide (SiO2), PECVD oxide (TEOS), silicon nitride (Si3N4) and BN.
Table 7.2 Typical polishing selectivities of silicon to other materials
| Material | SiO2 | TEOS | Si3N4 | BN |
|---|---|---|---|---|
| Selectivity | ~ 3-4 | ~ 2-3 | ~ 10-100 | ~ 50-100 |
The layer transfer process by a chemical etching approach is schematically shown in Fig. 7.3. The process is commonly termed "BESOI" (Bonding and Etch-back Silicon-On-Insulator). To transfer a single-crystalline silicon layer onto a handle wafer that is on the top of an etch-stop layer in a device wafer, the two wafers are first bonded to each other followed by an annealing step to strengthen the bond, see Fig. 7. 3(a) . Then the entire device wafer in a bonded pair is thinned by grinding and polishing to leave silicon of a few tens of microns followed by chemical etching until the etching is stopped by the etch-stop layer (Fig. 7.3b). During the etching process the handle wafer is protected by a coated mask layer. The etch-stop layer is then removed selectively. The thin and uniform device layer has thus been transferred onto the desired handle wafer (Fig. 7.3c).
The etch-stop performance can be described by the etch selectivity (etch-rate ratio) S of silicon to the etch-stop layer:
[7.1]
where Rsi is the etch rate of silicon and Re-s is the etch rate of the etch-stop. S = 1 corresponds to the case of no etch selectivity.
One method to evaluate the etch-stop efficiency is to measure the maximum etch step across the etch-stop and non-etch-stop boundary such as in the case that the etch-stop is formed by an ion implantation (7.7), see Fig. 7. 4 . This approach appears to be more meaningful since in this case the etch rate is likely to vary with the implant profile. The maximum etch step is observed when the etch-stop layer has been totally etched off. From a practical point of view, the maximum etch step is a critical quantity since it determines the acceptable thickness variation of the device wafer after grinding and polishing prior to the etch back. For example, if the maximum etch step is 3 , the allowable thickness nonuniformity of the device wafer after the usual mechanical thinning procedure should be less than 1.5 . Obviously, the average etch selectivity S can be derived from the effective etch-stop layer thickness d and the maximum etch step H as:
[7.2]
where t is the etch time for reaching the maximum etch step.
7.2.1 Aqueous alkaline etchants
Aqueous alkaline solutions are commonly used anisotropic silicon etchant. There are two categories of the etching system: 1) pure inorganic aqueous alkaline solutions such as KOH, NaOH, CsOH , NH4OH, etc. and 2) organic alkaline aqueous solutions most commonly are EDP (ethylenediamine-pyrocatechol-water),TMAH (tetramethyl ammonium hydroxide) and hyrazine. An electrochemical model for the reaction mechanisms has been suggested and is believed to be useful for all types of alkaline solutions (7.8):
It is a redox (oxidation and reduction) process and the key reacting species is the HOH/OH- redox couple in the etching solution.
In the oxidation reaction, a silicon atom is removed from the surface by reaction with four OH- ions:
[7.3]
The neutral Si(OH)4 can readily diffuse away from the silicon surface in the solution. The four free electrons which are generated from the above reaction are located in the silicon very close to the surface.
In the reduction reaction, these electrons leave the silicon surface and react with HOH molecules close to the silicon surface:
[7.4]
Only these OH- ions which are generated at the silicon surface are considered as the main reacting species. The OH- ions from the bulk of the etching solution experience a repulsive force from the negatively charged silicon surface and therefore do not play a major role in the reaction. The negative charges on the silicon surface originate from the higher Fermi level of the HOH/OH- couple than that of the silicon in the etching solution.
For aqueous KOH solutions with a concentration between 10-60% the etch rate of normally-doped silicon can be calculated by:
[7.5]
where Ea=0.595 eV and ko=2480 µm/h.(mol/liter)-4.25 (for silicon (100) surface) and Ea=0.60 eV and ko=4500 µm/h.(mol/liter)-4.25 (for silicon (110) surface). The etch rate of (100) silicon as a function of KOH concentration at a temperature of 72ºC is shown in Fig. 7.5. It can be seen that at high KOH concentrations the silicon etch rate becomes limited by the water concentration. Fig. 7. 6 is an experimental diagram of the etch rate as a function of temperature on (100) silicon wafers in various KOH solutions.
The above reaction model indicates that change in OH- concentration in the bulk of etching solutions causes only little change in the etch rates and that the cations in different etching solutions, K+, Na+, Cs+ and (NH)4+, make almost no difference in the etching behavior. The selection of the etching solutions is mainly determined by the concerns of etch selectivity, IC process compatibility, handling and anisotropy, cost, etc. for a specific application.
7.2.2 Etch selectivity of aqueous alkaline solutions
The etching reaction of silicon oxide can be described as (7.8):
[7.6]
According to the above equation, the silicon oxide etch rate depends on the concentration of ions in the bulk of the etching solution. The SiO2 etch rate as a function of KOH concentration and temperature is plotted in Fig. 7.7. A linear dependence on the molar KOH concentration is shown and the maximum etch rate occurs at ~35 % KOH. At higher concentrations the etch rate decreases with the square of the water molar concentration indicating that water plays a role in the reaction. The reason is as follows: at pH values larger than 2.8, a negative charge builds up on the oxide surface in the KOH solution hindering the diffusion of OH- ions but not the neutral water molecules to reach the oxide surface.
Fig. 7.8 shows the etch selectivity of (100) silicon to silicon oxide as a function of temperature in KOH and EDP solutions. The etch selectivity in EDP is about two orders of magnitude larger than that in KOH solutions.
EDP is a popular aqueous organic alkaline solution for silicon anisotropic etching. The composition of the most commonly used EDP solution is:
Ethylenediamine (NH2(CH2)2NH2) : pyrocatechol (C6H4(OH)2) : water (H2O) : pyrazine (C4H4N2) = 1.0 liter: 160 g : 133 ml : 6 g.
The etch rate of (100) silicon in the EDP solution has been shown in Fig. 7.5. The etch rate of SiO2 as a function of temperature in EDP and KOH solutions is shown in Fig. 7.9. The three orders of magnitude slower etch rate in EDP than that in KOH is attributed to the three orders of magnitude smaller OH- ion concentration (0.0034 mol/liter) in EDP than that of KOH solution (5-10 mol/liter).
For process compatibility with main-stream IC fabrication and for non-toxicity, an etch solution based on ammonium hydroxide-water and quaternary ammonium hydroxide-water solutions have been introduced recently for silicon etching. The most commonly used etch solution of this kind is TMAH (tetramethyl ammoniumhydroxide, (CH3)4NOH).
The dependences of (100) silicon and silicon oxide etch rates in TMAH on concentration and temperature are shown in Fig. 7.10 and 7.11, respectively (7.9). The etch selectivity of (100) silicon to silicon oxide is slightly smaller than that in EDP.
7.2.2.2. P++ silicon (7.10, 7.11)
It has been found that the silicon etch rates of all aqueous alkaline etchants are reduced significantly if silicon is doped with boron with concentrations exceeding 2X1019 cm-3, see Fig. 7.12 for (100) silicon.
This etch-stop effect can be explained according to the etching mechanisms discussed above. At boron concentrations greater than 2.2X1019 cm-3 silicon becomes degenerated. The four electrons generated by the oxidation reaction [7.5] have a high chance to recombine with holes which are available in very large quantity in the silicon. As a results the four electrons are no longer available for the subsequent reduction reaction [7.6] which is required to continue the etching process. The only available thermal equilibrium electron concentration n=ni/p2 determines the silicon remaining etch rate. Since the hole concentration p originating from the heavily doped boron or any other III group impurities is so high the remaining number of the electrons is small. Clearly, it is the hole concentration in silicon rather than the boron or any other elements of III group concentration which determines the etch rate. Experimental results show that ~8X1019 cm-3 and 1X1020 cm-3 of boron doping are required to have a etch selectivity of 100 of lightly doped (100) silicon to the heavily boron-doped silicon in EDP and 10% KOH, respectively. At higher KOH concentrations the etch selectivity is lowered mainly due to the slower etch rate of lightly doped silicon in the KOH solutions. On the other hand, addition of isopropyl alcohol (IPA) into KOH solution can increase the etch selectivity due to its ability to adjust the relative water concentration in the etchant without significantly affecting the pH value.
It has been found that carbon-doped silicon exhibits a significantly reduced etch rate in EDP. Fig. 7.13 shows the experimental etch selectivity of a carbon-implanted (100) silicon in EDP and 45% KOH at 85ºC as a function of the carbon peak concentration (7.12). At carbon peak concentration of 1.5X1021 cm-3 the etch selectivity reaches 1000 in EDP.
Since the carbon concentrations are not sufficient to form a continuous SiC layer (7.13), the etch-stop effect of carbon-doped silicon layer appears to arise from the chemical characteristics of nonstoichiometric SixC1-x alloy formed by randomly distributed implanted carbon atoms with the host silicon atoms (7.7).
It should be mentioned that CVD silicon carbide (SiC) layers as well as SiC layers formed by implantation show almost no etch rate at all in KOH, EDP or any other alkaline solutions (7.14).
7.2.2.4. Germanium-doped silicon
Germanium-doped silicon forms a SixGe1-x alloy which also exhibits an etch-stop effect. A MBE (Molecular Beam Epitaxy) Si0.7Ge0.3 layer grown at 500ºC showed a etch selectivity of 17 to normal (100) silicon before annealing at 850ºC (7.15). The germanium concentration in the layer was 1.5X1022 cm-3. After annealing the etch selectivity was reduced to 10-12. The etch-stop effect is believed to be associated with the strain induced by the relatively larger atom size of germanium.
SixGe1-x layers formed by germanium implantation in silicon shows higher etch selectivities than MBE or CVD grown SixGe1-x layer (7.7). When (100) silicon is implanted with Ge at 200 keV with a dose of 5X1015 cm-2 which corresponding to a peak Ge concentration of 3.1X1020 cm-3 the etch selectivity already reaches 12. This result indicates that an amorphization of the implanted layer is a factor in determining the etch-stop efficiency in germanium implanted samples (7.15).
7.2.2.5. Nitrogen-implanted silicon
Nitrogen-implanted silicon can form an etch-stop layer buried in the silicon with a dose of 1X1017 cm-2 at 140 keV which corresponds to a nitrogen peak concentration of 6X1021 cm-3 which is 10 times lower than necessary for forming a continuous silicon nitride (Si3N4) layer (7.10). High annealing temperatures tend to degrade the etch-stop efficiency indicating that the electron traps introduced by the nitrogen implantation may play an important role in recombining the four electrons necessary for the silicon etching.
CVD silicon nitride (Si3N4) layers show no measurable etch rate in KOH, EDP and any alkaline solutions. Therefore, it can be considered as a perfect masking material for practical applications.
7.2.3 Silicon anisotropic etching
The above alkaline solutions etch silicon anisotropically. The experimental results of the etch rates of (100), (110) and (111) silicon in EDP solution as a function of temperature are shown in Fig. 7.14. A similar curves can be obtained for KOH solutions. For EDP the following etch rate ratios hold :
The etch rate ratio of (110):(100):(111) = 50:30:1 at 100ºC;
The etch rate ratio of (110):(100):(111) =160:100:1 at 30ºC (room temperature).
The anisotropy is considered as a results of the lower surface Si-OH bonds per unit cell on (111) than that on (100) and (110) leading to a higher energy to break the backbonds of the (111) surface silicon atoms in the etchant (7.8).
The anisotropic etch effect can be employed to generate V-grooves with a self-adjusting depth in (100) silicon wafers based on openings in appropriate mask such as oxide layer. The (111) planes in silicon form an angle of 54.7o with the (100) plane. If we neglect the etching of the (111) planes the width W of the oxide window of the pattern approximately determines the final depth of the etched groove d, see Fig. 7.15 :
[7.7]
7.2.4 Silicon isotropic etching
The most commonly used isotropic silicon etch solution is HF-HNO3 solution in acetic acid (CH3COOH) (7.17). The nitric acid oxidizes silicon to form silicon oxide which is then dissolved by HF :
[7.8]
[7.9]
H2SiF6 is removed by dissolving in the solution. Acetic acid is a buffering agent which reduces the dissociation of nitric acid.
The etch solution commonly termed "1-3-8" etch can be used to etch heavily doped silicon (p++ or n++) about 100 times faster than that of normal silicon:
HF(49%) : HNO3(30%) : CH3COOH (100%)= 1: 3: 8 (in volume).
The etch rate of silicon with a boron concentration greater than 7X1018 cm-3 is 2 µm/min (7.18). It decreases to ~0.02 µm/min at concentration of 3X1017 cm-3.
The etch rate of silicon with a phosphorous concentration greater than 8X1018 cm-3 is 2.9 µm/min. It decreases to 0.16 µm/min at concentration of 5X1017 cm-3.
Since the oxidation of lightly doped silicon is much slower than that of heavily doped silicon, the rate determining step in the etching of lightly doped silicon by the 1-3-8 etch appears to be the oxidation while in heavily doped silicon the rate determining step becomes the HF diffusion which is fast (7.18).
Thinning of entire silicon wafers of bonded pairs for device layers in submicron thickness with a variation less than 10% is usually achieved by a layer transfer approach in which a predetermined thin and uniform silicon layer on a silicon device wafer is transferred onto a desired substrate (handle wafer). The wafer to which the silicon layer is transferred does not necessarily have to be a bare or oxidized silicon wafer but can also be some other material such as quartz, sapphire or diamond. The predetermined thin and uniform silicon layer can be created for example, by epitaxial layer growth or ion-implantation. Layer transfer is commonly realized by bonding and subsequent chemical etch-back of the device wafer in which the predetermined thin and uniform silicon layer is on the top of a built-in etch-stop. The most popular etch-stop layers include B/Ge, C and oxide. Recently, another layer transfer method has been demonstrated in which a hydrogen-implanted wafer is bonded to a handle wafer and the implanted layer is split from the handle wafer during annealing (7.4).
7.3.1 Layer transfer by bonding and etch-back
As described above heavily boron-doped silicon exhibits a significantly lower etch rate than that of normal lightly doped n or p type silicon in alkaline aqueous solutions. Therefore, the use of a B etch-stop is the most frequently used method for thinning the device wafer in a bonded silicon pair. However, there are problems associated with heavy doping of boron in silicon, mainly, outdiffusion and misfit dislocations.
Boron is an electronically active impurity in silicon and has a relatively high diffusivity at normal heat treatment temperatures. The thermal budget for bonding, annealing, oxidation or activation of implanted boron is therefore limited.
The size of a boron atom is smaller than that of a silicon atom: when in tetrahedral covalent bonding conditions, the radii of silicon and boron are 1.17 Å and 0.88Å, respectively. Substitutional placement of boron in the silicon lattice causes a tensile stress locally and a shrinkage collectively. The equilibrium lattice constant of the boron doped layer becomes mismatched with the silicon substrate and stress along the interface increases with the dopant concentration. If the highly boron doped layer is sufficiently thin, the mismatch strain can be accommodated elastically in such a way that the lattice parameters parallel to the interface with the substrate remain unchanged. The critical thickness tc is given by (7.19, 7.20):
[7.10]
where b is the length of the Burger's vector (3.84 Å for 60°-type dislocations in silicon), is the angle between the dislocation line and its Burger's vector, is the angle between the slip direction and that line in the interface plane which is normal to the line of intersection between the slip plane and the interface (q = l = 60º), and f is the misfit (7.21):
[7.11]
where is an experimental constant = -1.49 Å, NB is the boron concentration in dimensionless atomic fractions (obtained by multiplying the volume concentration by the atomic volume of silicon 2 X10-23 cm-3 and asi is the silicon lattice constant (5.4307Å at 25ºC).
However, if the doped layer is thicker than tc, the stress will be partly released by a plastic deformation of the silicon crystal in the form of misfit dislocations. Consequently, the device layer epitaxially grown on top of the etch-stop layer will be defective due to threading dislocations.
The strain and thus the stress may be compensated by codoping with germanium which has a covalent radius (1.22 Å) larger than that of silicon and which is electrically inactive. Under the assumption that the total strain can be represented by a linear superposition of the individual strains caused by germanium and boron, the misfit f is derived to be (7.21):
[7.12]
The strain is fully compensated when the ratio of the two dopant concentration in silicon reaches:
[7.13]
where NB and NGe are atomic concentrations of B and Ge in silicon, respectively.
The following is an example of SOI preparation by using device wafers with a B/Ge etch-stop layer (7.22). Wafers with an epitaxially grown B/Ge etch-stop layer and a nominally undoped silicon layer on top were bonded to an oxidized silicon wafer. Annealing at 650-800 °C was performed. After grinding and polishing to remove most of the substrate from the epi-wafer, EDP was used to etch off the remaining 10-30 µm of the silicon substrate. The etch was stopped when a hole concentration of ~8X1019/cm3 in the B/Ge layer was approached. The etch selectivity S1 is about 100 at this stage. The B/Ge layer was then etched off by an 1-3-8 etch which has also a etch selectivity S2 of about 100. Therefore, the final thickness variation of the device layer is a factor of S1 x S2 smaller than the original thickness variation of the silicon layer after grinding :
[7.14]
In this case, S1 x S2 greater than 10,000 was obtained. The SOI layer obtained by the strain compensated etch-stop method shows thickness uniformity better than 100Å and excellent smoothness of its surface. A low misfit dislocation density of ~1-20/cm 2 was achieved. The residual doping in the SOI film was below 5X1016/cm3 and excellent carrier lifetimes have been measured in these films (7.22).
Another approach which does not require an epitaxial growth in forming a device layer employes MeV boron implantation (7.23). Using high implant energy the profile of implanted boron concentration becomes much sharper than that in low energy case so that the surface boron concentration is reduced. Fig. 7.16 shows the SIMS (Secondary Ion Mass Spectroscopy) profile of the boron implant with 6X1015 cm-2 at 2.5 MeV. In order to have a Si/thermal SiO2 interface the implanted wafer was slightly oxidized (250-500 Å oxide). After bonding of the boron implanted wafer to an oxidized wafer and subsequent annealing (at as low a thermal budget as possible to avoid excess boron outdiffusion, e.g. 800ºC, 10 min), the device wafer of the bonded pair was thinned by grinding and EDP etching to reach the etch-stop. The remaining silicon layer was 3.5 µm. The etch-stop was then removed by 1-3-8 etch followed by thermal oxidation and subsequent oxide strip to further thin the SOI layer down to a desired thickness. However, the multiple-oxidation generated a substantial density of oxidation induced stacking faults.
By another MeV boron implant (6X1015 cm-2 at 1.6 MeV) into the remaining 3.5 µm, a second etch-stop was created, shown also in Fig. 7.16. The second etch was stopped at the location "2" in Fig. 7.16 and the etch-stop was then removed by 1-3-8 etch at the location "3" followed by a short wet oxidation and subsequent oxide strip to thin the SOI layer down to a ~0.5 0.004 µm. Since the defective remaining tail of the second boron implant in the SOI layer was removed by the short oxidation step, low defect density has been achieved.
7.3.1.2 Carbon-implanted etch-stop
Carbon is an electrically inactive substitutionally dissolved impurity in silicon. Also, implanted carbon forms strong gettering sites in silicon and can act as sink for implantation-induced excess silicon self-interstitials and thus retard the formation of dislocation loop (7.24). As discussed above, Si layers implanted with carbon at conventional energies ( 200 keV) and doses (1-3X1016 cm-2) act as effective etch-stop. The etch-stop efficiency degrades with annealing temperature and virtually disappears at temperatures greater than 900ºC (7.14). Use of a C etch-stop for ultrathin SOI preparation was reported (7.25).
4-inch, p-type, 5-10 cm, CZ (Czochralski-grown) (100) silicon wafers were used. The wafers were implanted with a carbon dose of 3X1016 cm-2 at an energy of 190 keV. This implantation process leaves the wafer surface layer of Si, about 900Å thick, to be crystalline, followed by a deeper amorphous region containing a high carbon concentration. SIMS measurements revealed that the peak carbon concentration was 1.3X1021 cm-3 and was located at 0.548 µm below the wafer surface, see Fig. 7.17. It was found that after annealing at 1100ºC in argon for 1 h, the carbon concentration in the near surface region (~913Å thick) was reduced to below the detection limit of the SIMS measurements, see Fig. 7.17 . This low carbon concentration region was termed a "carbon-denuded zone" (7.25).
The mechanism for the formation of the carbon-denuded zone is as follows: carbon diffuses from the region near the silicon surface into the high carbon concentration region where a high concentration of carbon precipitates has formed during the 1100ºC annealing. The as-implanted material has a buried amorphous layer deeper down, while the near surface Si layer is crystalline. Therefore, after recrystallization at 1100ºC there is an abundance of low energy carbon precipitates nucleation sites in the recrystallized region, since the Si crystal contains s density of point defects. This factor, in addition to the high carbon supersaturation in the region, lead to rapid carbon precipitate nucleation and growth. In the silicon crystal near surface layer, the carbon supersaturation is much lower and the material is crystalline in the first place, leading to a negligible carbon nucleation rate. As annealing time elapses, the supersaturated carbon in the deeper region will be depleted by carbon precipitate growth and the surface region supersaturated carbon will also be depleted by indiffusion into the deeper region where the carbon atoms are incorporated in growing carbon precipitates.
The carbon-implanted silicon wafer was bonded to an oxidized silicon wafer. Because of the degradation of the etch-stop efficiency of the carbon-implanted layer with temperature, the post-bonding annealing to increase the bonding strength was performed at 300 for 42 h. The bonding strength after annealing was found to be higher than 800 mJ/m2 and was adequate for grinding and etching for removal most of the silicon bulk of the device wafer* to leave the silicon layer with 1.5 0.5 µm thick. The wafer was then etched in EDP at 90ºC resulting in a SOI layer of 5275 14 Å in thickness. Thermal oxidation was employed to oxidize about 4400 Å carbon-precipitated silicon which was on top of the wafers. The thermally grown oxide was then removed by dip in HF aqueous solution. The ultrathin (less than 900 Å) SOI layer with a thickness variation of 50 Å was finally realized in which the carbon concentration was at or below the SIMS measurement limit.
7.3.1.3 Oxygen-implanted etch-stop
To utilize the excellent etch selectivity of silicon to silicon oxide in alkaline aqueous solutions, an oxygen-implanted layer in silicon has been employed as an etch-stop in preparation of SOI materials. The commercially available SIMOX wafers provide a BOX (Buried Oxide) layer as the etch-stop (7.26).
Standard SIMOX (oxygen dose of 1.8X1018 cm-2, energy of 190 keV) can provide ultrathin uniform (0.230.005) µm SOI films in volume but suffers from higher defect density (>1X105/cm2), limited thickness of both SOI (0.03-0.5 µm unless followed by additional epitaxial growth) and BOX (0.05-0.6 µm) layers, limited process flexibility and poor quality of BOX layers and their interfaces. Among them the most difficult and complicated problems are related to the BOX layer. The coalesced oxide from implanted oxygen appears to behave quite differently from thermal oxide. The BOX layer of SIMOX has silicon inclusions, conducting pipes and pinholes, charge traps and defects distributed through the BOX bulk as well as located at its interface, contaminations, low oxide breakdown voltage and nonuniform thickness. The problems become worse for thinner BOX layers. However, the BOX layer has been shown to still be adequate as an excellent etch-stop.
Transfer of commercially available SIMOX layers onto thermally oxidized Si wafers by SIMOX wafer bonding and etch-back with the BOX/SIMOX as an etch-stop layer can produce high quality SOI combining advantages of SIMOX and bonding technologies and avoiding some of their respective problems (7.26). Especially, the thermal oxide on the handle wafer can be processed prior to bonding which is very attractive for applications such as radiation-hard SOI materials.
Since there is no problems associated with outdiffusion and degradation of etch-stop efficiency of the BOX layer, the high temperature (e.g., 1100ºC) annealing is allowed to strengthen the bond. To reduce the dislocation density in the SOI layer and lower the fabrication cost, low dose SIMOX can be used (7.27). For example, oxygen implantation at an energy of 120 keV with a dose 4X1017 cm-2 can form a continuous BOX of 800 Å thick and 2150 Å SOI layer after 1320ºC, 6 h annealing in the gas mixed argon with oxygen. The dislocation density is reduced to less than 103 cm-2. Comparison of the standard and typical low dose SIMOX is listed in Table 7.3.
Table 7.3 Comparison of standard and typical low dose SIMOX
| Implant energy (KeV) | Implant dose (cm-2) | Si thickness (Å) | BOX thickness (Å) | Dislocation Density (cm-2) | |
|---|---|---|---|---|---|
| Standard SIMOX | 190 | 1.8E18 | 2300 | 4000 | >1X1015 |
| Low dose SIMOX | 120 | 4E17 | 2150 | 800 | ~ 1X103 |
7.3.1.4 SiC etch-stop for transfer of SiC layers
Single- or polycrystalline §-SiC (3C-SiC) layers can be produced on silicon substrates by chemical vapor deposition (7.28). SiC is an inert material in silicon etchants therefore it can be transferred onto oxidized silicon or other desired substrates by bonding and etch-back using the surface device layer of SiC itself as an effective etch-stop (7.29). An example is as follows.
Silicon wafers covered with SiC are termed "SiC/Si wafers" in brief. After standard RCA cleaning the SiC/Si wafers were oxidized at 1050°C in dry oxygen to grow 250-1000 Å oxide on the SiC layers. In order to enhance hydrophilicity of mating wafer surfaces, both the oxidized SiC/Si wafers and the oxidized handle Si wafers were boiled in nitric acid at 100°C for 10 min and were rinsed in deionized water. The oxidized SiC/Si wafers were then bonded at room temperature to the Si wafers covered with 1 µm thermal oxide.
Atomic force microscope (AFM) measurements have shown that the mean surface roughness (Ra) of the SiC layer covered with 500 Å oxide is about 23 Å and is much higher than the maximum value of ~5 Å required for bubble-free spontaneous room temperature bonding. The maximum peak-to valley value of the SiC surface roughness is about 226 Å. It has been found that even with the mating oxidized Si surface with an Ra of only about 1.5 Å, the wafers require external force in order to bond at room temperature. A Teflon bar was used to press the backside of the room temperature-contacted pairs to allow bonding to occur.
The bonded wafers were then annealed in air at 900°C for 2 h. After annealing the wafer pairs were lapped to remove silicon oxide ( and some SiC) from the back of the silicon substrate with the SiC layer. Finally, the silicon substrate of the SiC layer was etched in 13.5% KOH at 75°C for ~12 hrs while the oxidized Si wafer was protected by 1 µm oxide from KOH etching. The etching was stopped when the SiC layer was reached and the SiC layer was transferred onto the oxidized wafers.
7.3.1.5 Porous silicon etch-release layer
This method makes use of the possibility of epitaxial growth of a single crystalline silicon layer on top of a porous silicon surface and the high etch selectivity between the porous and the expitaxial silicon layers in a HF-H2O2-H2O solution (7.30). The process flow is schematically shown in Fig. 7.18.
In a solution of HF (49%) : C2H5OH (100%) = 2:1 at 7 mA/cm2, a P-type silicon (100) wafer with resistivity of 0.01-0.02 was anodized to form ~12 µm porous silicon layer on the surfaces. After oxidation of the porous silicon in O2 at 400°C for 1 h to passivate the pore walls and removing the the oxide from the surface, ~0.5 µm single crystalline silicon layer was epitaxially grown on the porous surface with a mixture of SiH2Cl2 and H2 at 900°C and 80 Torr. This device wafer was thermally oxidized to grow 1000 Å oxide and was bonded to a handle oxidized silicon wafer covered with 5000 Å oxide (Fig. 7.18a). After annealing at 800°C for 2 h in N2 the device wafer was thinned by grinding to expose the porous silicon on the entire wafer surface. Finally the porous silicon layer was selectively etched off by HF (49%) : H2O2 (30%) = 1:5 solution (Fig. 7.18b). The etch selectivity of porous silicon to bulk silicon was ~10,000 in the solution. The extremely high etch selectivity leads to thickness variation of the transferred silicon layer of about 280Å by using this one etch-stop method (Fig. 7.18c). This method can also be used to transfer the epitaxial silicon layers onto other desired substrates.
7.3.2 Layer transfer by bonding and layer-splitting
Recently, another layer transfer technology was reported (7.4). The basic process flow is schematically shown in Fig. 7.19.
The first step (Fig. 7.19a) is to implant hydrogen ions into the device silicon wafer. The implant dose is 2X1016 to 1X1017 cm-2. The implant energy is determined by the required final device layer thickness. The thickness depends only on the implant energy with about 90 Å/keV in silicon. Table 7. 4 lists the thickness of the device layer as a function of the hydrogen ion implant energy (7.28).
Table 7.4 Relationship of the device layer thickness and the hydrogen ion implant energy
| H+ implant energy (KeV) | 10 | 50 | 100 | 150 | 200 | 500 | 1000 |
|---|---|---|---|---|---|---|---|
| Device layer thickness (µm) | 0.1 | 0.5 | 0.9 | 1.2 | 1.6 | 4.7 | 13.5 |
In order to obtain a high quality Si/SiO2 interface in the final SOI structure, the device wafer is thermally oxidized before implantation.
The implanted device wafer and a handle silicon wafer with or without oxide are cleaned in RCA solutions and the surfaces of both wafers becomes good hydrophilic. They are then bonded at room temperature (Fig. 7.19b).
The bonded pair is annealed at 400-600°C. During annealing the bonding strength of the pair is greatly enhanced. Hydrogen is a structure breaking element and can embrittle silicon even at room temperature (7.29). Hydrogen in silicon can result in formation of micro-cracks or platelets lying parallel to the implanted surface. If sufficient hydrogen reaches the micro-crack a larger crack or bubble can be formed extending parallel to the bonding interface. The H+ implanted layer bonded to the handle wafer is split off from the device wafer at the mean H+ ion penetration depth during the annealing (Fig. 7.19c). The remaining device wafer can be recycled for using as a handle wafer later on. The bonding strength between the transferred silicon layer and the handle wafer is further enhanced by a second annealing at 1100°C.
A final light CMP polishing removes a few hundred Å from the top surface and results in a smooth surface with a mean surface microroughness of <1.5 Å and with a thickness variation of ~100 Å (Fig. 7.19d).
Since hydrogen ions are very light, the implantation profile is relatively sharp and the atomic displacements in the implanted silicon is minimized which result in a low defect density in the device layers which is further reduced by the high temperature annealing after the splitting.
7.3.3 Layer transfer by bonding and lateral etching
The etch selectivity of AlAs layer to AlxGa1-xAs film is as high as 108 (for x 0.4) in a 10% aqueous HF solution. This extremely high etch selectivity has been employed to release a epitaxial film from its growth substrate by undercutting an AlAs layer (7.33).
The typical process is schematically shown in Fig. 7.20. A multilayer AlxGa1-xAs film was epitaxially grown on an AlAs layer on GaAs substrate. The AlAs release layer is lattice matched to GaAs and typically 500 Å thick. A black wax (Apiezon W) was applied to the epitaxial film, which is a strip with width less than 20 mm, by melting a pellet onto its surface at 125°C and flattening it to a thickness of 0.1-0.5 mm by pressing at 75°C. After removing the wax from the edges of the buried AlAs layer the sample was immersed in a 10% aqueous HF solution at 0°C (Fig. 7.20a). The epitaxial film was undercut and released completely from its substrate by lateral etching of the AlAs layer. After rinsing in DI water, the wet epitaxial film was then placed on a desired substrate which was treated to be hydrophilic. After squeezing out the excess water from the bonding interface, the remaining water escaped to the edges by Poiseuille flow and the gap between the film and the substrate decreased until short range van der Waals forces and hydrogen bridging bonds hold the two pieces together (Fig. 7.20b). The wax was then removed by rinsing in trichloroethylene leaving the epitaxial film bonded to the substrate.
As long as the film-substrate interfacial energy 2 is less than the sum of substrate-water and water-film surface energies, the water will tend to be forced out as the film and substrate surfaces coalesce together:
[7.15]
So far only relatively narrow strips (< 20 mm) of expitaxial films have been transferred to new substrates with more favorable properties than the growth substrates. The main reason is the difficulty of the gas product of the undercut etching reaction to diffuse off the extremely narrow gap so the etch rate goes down drastically as the strips get wider. It is conceivable that an entire epitaxial film on a substrate wafer may be transferred by bonding and lateral etching of a release layer with the help of the mismatch thermal stresses between the new substrate of the film and the growth substrate so as to lift up the corners of the expitaxial film during undercutting. However, it needs to be experimentally verified. Alternatively, a method has been developed in which a system of sufficiently densely spaced grooves allows the lateral access of the etching solution so that layers over whole wafers can be transferred in forms of many small areas separated by the grooves (7.34).
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