Conferences & Workshops

1. "Web search using mobile cores: Quantifying and mitigating the price of efficiency," 37th IEEE/ACM International Symposium on Computer Architecture (ISCA), June 2010.
   
2. "Phase change memory: An architecture and systems perspective," Workshop on Emerging Memory Technologies (EMT), in conjunction with ISCA-37, June 2010.
   
3. "Architecting phase change memory as a scalable DRAM alternative," 36th IEEE/ACM International Symposium on Computer Architecture (ISCA), June 2009.
   
4. "CPR - Composable performance regression for scalable multiprocessor models," 41st IEEE/ACM International Symposium on Microarchitecture (MICRO), November 2008.
   
5. "Efficiency trends and limits from comprehensive microarchitectural adaptivity," 13th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2008.
   
6. "Roughness of microarchitectural design topologies and its implications for optimization," 14th IEEE International Symposium on High Performance Computer Architecture (HPCA), February 2008.
   
7. "Methods of inference and learning for performance modeling of parallel applications," 12th ACM Symposium Principles and Practice of Parallel Programming (PPoPP), March 2007.
   
8. "Statistical inference for efficient microarchitectural analysis," Boston Area Architecture Workshop (BARC), January 2007.
   
9. "Illustrative design space studies with microarchitectural regression models," 13th IEEE International Symposium on High-Performance Computer Architecture (HPCA), February 2007.
   
10. "Statistical inference for efficient microarchitectural and application analysis," IEEE/ACM International Conference for High Performance Computing, Networking, Storage, and Analysis (SC), November 2006.
    
11. "Poster: Statistical inference for efficient microarchitectural and application analysis," IEEE/ACM International Conference for High Performance Computing, Networking, Storage, and Analysis (SC), November 2006.
    
12. "Accurate and efficient regression modeling for microarchitectural performance and power prediction," 12th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2006.
    
13. "Statistically rigorous regression modeling for the microprocessor design space," Workshop on Modeling, Benchmark, and Simulation (MoBS) in conjunction with ISCA-33, June 2006.
    
14. "Effects of pipeline complexity on SMT/CMP power-performance efficiency," Workshop on Complexity Effective Design (WCED) in conjunction with ISCA-32, June 2005.
    
15. "Performance models for evaluation and automatic tuning of symmetric sparse matrix-vector multiply," 33rd International Conference on Parallel Processing (ICPP), August 2004.
    
16. "Optimizations and bounds for sparse symmetric matrix-vector multiply," SIAM Conference on Parallel Processing for Scientific Computing, March 2004.
    
17. "Poster: Automatic performance tuning of sparse matrix kernels," SIAM Conference on Computational Science and Engineering, February 2003.
    
    
    

Technical Panels

1. "Mega-servers vs micro-blades for data centers," Architectural Concerns in Large Datacenters (ACLD), in conjunction with ISCA-37, June 2010.
   
2. "Phase change memory: An architecture and systems perspective," Emerging Technologies Panel, International Symposium on Nanoscale Architectures (NANOARCH), in conjunction with DAC-47, July 2009.
   
3. "Architecting phase change memory as a scalable DRAM alternative," New Memory Technology Panel, 36th IEEE/ACM International Symposium on Computer Architecture (ISCA), June 2009.
   
   
   

Tutorials

1. "Learning and inference tutorial (LIT) for large design and parameter spaces," 13th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2008.
   
2. "Inference and learning for large scale microarchitectural analysis," 34th IEEE/ACM International Symposium on Computer Architecture (ISCA), June 2007.
   
   
   

Invited & Other

1. Intel Corporation, Hudson MA, August 2010.
   
2. Harvard University, Cambridge MA, August 2010.
   
3. University of California, Berkeley CA, August 2010.
   
4. Intel Corporation, Santa Clara CA, July 2010.
   
5. Google, Mountain View CA, July 2010.
   
6. Stanford Pervasive Parallelism Lab (PPL) Retreat, Santa Cruz CA, June 2010.
   
7. Lawrence Livermore National Laboratory, Livermore CA, May 2010.
   
8. University of California, Los Angeles CA, April 2010.
   
9. Princeton University, Princeton NJ, March 2010.
   
10. University of Southern California, Los Angeles CA, March 2010.
    
11. Duke University, Durham NC, March 2010.
    
12. Stanford University, Palo Alto CA, September 2009.
    
13. University of Texas, Austin TX, March 2009.
    
14. Swiss Federal Institute of Technology (ETH), Zurich Switzerland, March 2009.
    
15. University of Rochester, Rochester NY, March 2009.
    
16. Rutgers University, Newark NJ, March 2009.
    
17. Northwestern University, Evanston IL, March 2009.
    
18. University of Washington, Seattle WA, March 2009.
    
19. AMD Research, Bellevue WA, March 2009.
    
20. Microsoft Research Techfest, Redmond WA, February 2009.
21. Microsoft Research, Redmond WA, April 2008.
    
22. IBM Watson Research Center, Yorktown Heights NY, April 2008.
    
23. Intel Corporation, Santa Clara CA, September 2007.
24. Intel Corporation, Santa Clara CA, June 2007.
    
25. Intel Corporation, Folsom CA, June 2007.
    
26. Lawrence Livermore National Laboratory, Livermore CA, September 2006.
27. Harvard University Industrial Partnership Annual Meeting, Cambridge MA, October 2005.